turbo-blif

low-memory-usage BLIF (berkeley logic interchange format) parser.

	this	SIS	yosys	abc	pip blifparser	lorina	crates.io blif-parser	quaigh	libblifparse	spydrnet
top module, latches, LUTs	x	x	x	x	x	x	x	x	x	x
different latch types	x	x	x	x	-	x	x	-	x	-
usage of library gates / latches	x	x	x	x	-	-	x	-	-	~
empty lines, padding, and comments	x	x	?	x	-	x	x	x	x	x
quirk 1: allow omit .end and .model	x	x	?	-	?	?	?	-	-	?
'quirk' 2: \ to continue on next line	x	x	x	x	-	-	x	x	x	x
multiple models per file & sub-circuits	x	x	x	-	-	-	x	-	x	x
model attr: .clock	x	x	x	-	-	-	-	-	-	x
sub-file references	x	x	?	-	x	-	-	-	-	-
finite state machines (.start_kiss)	x	x	-	-	x	-	-	-	-	-
clock constraints (mostly for simulation)	soon	x	-	-	-	-	-	-	-	-
delay constraints	soon	x	-	x	-	-	-	-	-	-
full BLIF specification 1	soon	x	-	-	-	-	-	-	-	-
extension: "Black- & White-boxes" 2	soon	-	-	-	-	-	-	-	-	-
extension: .blackbox	soon	-	x	x	-	-	-	-	x	x
extension: .cname (EBLIF3 )	x	-	x	-	-	-	-	-	x	x
extension: .attr and .param (EBLIF3 )	x	-	x	-	-	-	-	-	x	x
extension: .conn (EBLIF3 )	x	-	x	-	-	-	-	-	x	x
extension: .barbuff (identical: .conn)	x	-	x	-	-	-	-	-	-	-

• the latest BLIF specification (dated July 28, 1992)
• all yosys BLIF extensions (supports reading of BLIF files generated with write_blif -iname -iattr -param -cname -blackbox -attr -conn)
• KISS state machines (which yosys doesn't even support)
• clock and delay constraints (yosys just ignores those)

If you found a program that generates non-standard BLIF attributes or keywords, please open a GitHub issue. We want to support all non-standard extensions.

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1. https://people.eecs.berkeley.edu/~alanmi/publications/other/blif.pdf ↩︎

2. https://people.eecs.berkeley.edu/~alanmi/publications/other/boxes01.pdf ↩︎

3. https://docs.verilogtorouting.org/en/latest/vpr/file_formats/ ↩︎